Demonstration of Power Enhancements on an Industrial Circuit through Delay Management of Non-critical Data Paths
نویسندگان
چکیده
On-chip power dissipation has become a fundamental design issue in high performance integrated circuits. A technique to significantly reduce the power dissipated in the non-critical data paths of an industrial circuit is demonstrated. The application of this technique with non-zero clock skew scheduling to the slower data paths is also described. Simulation results demonstrating the application of this technique to certain functional blocks of a high performance microprocessor are presented. A greater than 80% power savings is achieved in specific circuit blocks.
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